With deep sub-micron technology, chip designers are expected to create System-On-Chip (SOC) solutions by connecting different Intellectual Property (IP) blocks using efficient and reliable ...

HSI is a critical capability that now has the full attention of the Accellera PSWG and whose absence results in extra work for companies that want to adopt Portable Stimulus tools without some form of ...

Designing the hardware-software interface. Dealing with "bytes enables" in RTL verification. Automating the HSI design process across the entire dev team. The hardware-software interface (HSI) holds ...

In today’s semiconductor landscape, scale is becoming a bigger battleground—not only for chipmakers, but increasingly for hyperscalers, cloud giants, and other systems companies, too. They're all ...

From the earliest days of my career, when designing chips, I have always navigated the interface between hardware and software for semiconductor design in my roles. My initial chip designs included ...

Reusing parts of designs, or intellectual property (IP), has been a goal of engineering organizations for a long time. Obviously, it would be wonderful if once something is designed and works properly ...

Impulse Accelerated Technologies, Inc. announced the newest edition of its CoDeveloper” C to RTL design tools, which adds support for Altera's SOPC Builder and the Quartus II, Version 4.1 design ...

Hardware/Software Co-Verification is typically performed at a low level of abstraction, using an Instruction Set Simulation (ISS) model of a CPU in conjunction with a Verilog or VHDL model of the rest ...

A hardware interface specifies the plugs, sockets, cables and electrical signals that pass through each line between the CPU and a peripheral device or communications network. It also stipulates which ...