Abstract: For triple-level or quad-level 3D NAND flash memory, narrowing the Vth distribution of each state without influencing page program performance is one of the challenges. Considering this ...
Abstract: We present PLC (Penta-level cell, 5 bits/cell) NAND flash memory using 3D charge-trap-flash (CTF) cell. To achieve PLC cell distribution with proper cell read margin, program noise and short ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback